In a current addition type digital-to-analog converter (DAC), each of the bits in a digital signal is provided to a switch that controls current flow in a separate branch of the DAC. When a bit provided to one of the switches is “on”, the switch is closed, thereby enabling current to flow in the respective branch. The DAC can operate (to provide an analog output signal) by adding all of the currents flowing in each of the braches in response to all of the bits in the digital signal being provided to the DAC. A 10-bit current addition type DAC is discussed, for example, in Korean Laid Open Patent Publication No. 2000-0072961.
FIG. 1 is a schematic diagram showing a conventional 10-bit current addition type DAC having a current compensation circuit. Referring to FIG. 1, the 10-bit current addition type DAC includes a plurality of PMOS transistors MP1, MP2, . . . , MP36. The PMOS transistors MP1, MP2, . . . , MP36, are coupled to a current source PMOS transistor MPREF in a current-mirror configuration to provide respective outputs currents I, 2I, . . . , 32I, where 2I is twice the current I and 32I is 32 times the current I etc. A plurality of switches SW1, SW2, . . . , SW36 are connected between drain electrodes of the PMOS transistors MP1, MP2, . . . , MP36 and an output terminal OUT. The switches operate in response to the digital input signals D1, D2, . . . , D36. The lower 5 bits of the 10 bit input signal are applied to the switches SW1, SW2, . . . , SW5, whereas the upper 5 bits of the 10 bit input signal are decoded to provide 31 separate signals. The 31 separate signals are applied to the switches SW6, SW7, . . . , SW36 respectively.
The current addition type DAC further includes a current compensation circuit 10. The current compensation circuit 10 can regulate the currents flowing through the PMOS transistors MP1, MP2, . . . , and MP36 when the currents flowing through the PMOS transistors MP1, MP2, . . . , MP36 have abnormal amplitudes. The currents output by the PMOS transistors MP1, MP2, . . . , MP36 are coupled to turned-on switches and are added altogether and applied to an output resistance RO to develop a voltage across the output resistor RO. In particular, the voltage at the output terminal OUT is equal to the sum of a reference voltage VREF coupled to one terminal of the output resistor RO and the voltage at the output resistor RO. The DAC outputs an analog signal at the output terminal OUT corresponding to the digital input signals D1, D2, . . . , D36.
The ratios of the currents (i.e., I, 2I, . . . 32I) flowing through the PMOS transistors MP1, MP2, . . . , MP36 are determined by the respective sizes of the PMOS transistors MP1, MP2, . . . , MP36 so that the larger the transistor size, the larger the current that may flow when the transistor is turned on. For example, transistor MP36 may be 32 times larger than MP1 so that the current (32I) generated by MP36 is 32 times greater than the current generated by MP1. Thus, the chip size may increase when the current addition type digital-to-analog converter is implemented in an integrated circuit.
Referring again to FIG. 1, when the transistor size of the PMOS transistor MP1 coupled to the lowest bit D1 is assumed as 1, the transistor sizes of the PMOS transistors MP2, MP3, MP4 and MP5 are 2, 4, 8, 16, respectively, and the transistor sizes of the PMOS transistors MP6, . . . , and MP36 are 32. The size of each of the PMOS transistors MP1, MP2, MP3, MP4 and MP5 (corresponding to lower 5 bits of the digital signal) increases according to the expression 2k relative to the immediate lower order transistor. In particular, MP2 is twice as large as MP1, MP3 is twice as large as MP2, MP4 is twice as large as MP3, and MP5 is twice as large as MP4 so that the MP5 is 16 times are large as MP1. Further, the PMOS transistors MP6, MP7, . . . , and MP36 are each twice as large as MP5 (and 32 times larger than MP1).
In addition, it may be difficult to increase the precision (or accuracy) of the conventional DAC of FIG. 1, as the size of the DAC may increase significantly as the number of bits in the digital input increases. The total area needed for an N bit DAC can be expressed as the total number transistors needed for the DAC, where each of the transistors occupies a unit area (i.e., 1 unit area). For example, the area needed for a 10 bit DAC can be expressed as: (1+2+4+8+16)+(32×31)=1023 unit areas, where each of the areas represents the size occupied by the PMOS transistors MP1, MP2, . . . , MP36 respectively. Extending this expression to a higher resolution 12 bit DAC, the total area occupied by PMOS transistors can be expressed as: (1+2+4+8+16+32)+(64×63), or 4095 unit areas. Accordingly, when the structure shown in FIG. 1 is increased to provide a 12 bit DAC, the chip size of the DAC may increase by 4 times.
In the conventional DAC of FIG. 1, the transistors MP1, MP2, . . . , MP36 are connected to the reference transistor MPREF in a current mirror configuration. Thus, the transistor sizes of the PMOS transistors MP6, . . . , MP36 corresponding to upper bits of the digital input signal should be designed to have two times larger than the transistor size of the PMOS transistor MP5 corresponding to the upper most bit D5. The number of the PMOS transistors MP6, . . . , MP36 corresponding to upper bits of the digital input signal is 31, which causes an increase in the total chip size of the digital-to-analog converter when the transistor sizes of the PMOS transistors MP6, . . . , MP36 are designed to be 32 times larger than the transistor size of the PMOS transistor MP1 corresponding to the lower most bit D1.
Another current addition type DAC is discussed, for example, in Japanese Patent Laid Open Publication No. 1997-191252. The current addition type DAC of the above Japanese Patent Publication includes two current providers, and a transistor having a size, which acts as a current source, connected to a first current provider that is different from a transistor size of a transistor, which acts as a current source, connected to a second current provider. Thus, the chip size of the digital-to-analog converter may be reduced. Particularly, in the current addition type digital-to-analog converter of the above Japanese Patent Publication, the current provider includes a MOS transistor and a resistor connected to a source electrode thereof, and the switch to which an digital input signal is inputted is connected to a gate electrode of the MOS transistor. In addition, the ratio of the currents provided from the current provider is determined by the ratio of the resistances of the resistors connected to the MOS transistors of the current provider.